1. Field of the Invention
The invention relates to a word line driver for a memory, and more particularly to a dual power rail word line driver.
2. Description of the Related Art
Since process technologies have been scaled down, such as the deep sub-micron process, the layout area of a system on chip (SOC) has greatly been decreased. However, memory device reliability (e.g. static random access memory (SRAM)) in the greatly decreased sized SOC worsens due to low supply voltages, threshold voltage mismatch caused by process variations and so on. For example, a threshold voltage mismatch of a memory device is about 35 mV/sigma for 65 nm process. Moreover, such threshold voltage mismatch of a memory device is hard to estimate or simulate by a SPICE corner model, such as an SS (slow PMOS, slow NMOS), TT (typical PMOS, typical NMOS), FF (fast PMOS, fast NMOS), SF, or FS model.
In general, a 10 Mbit memory or greater, is common in an SOC. If a memory device of the SOC is operated with low supply voltage, read/write fail occurs due to threshold voltage mismatch among the memory cells. Furthermore, defect density of read/write fail is increased when supply voltage is decreased.
FIG. 1 shows a schematic diagram of an SRAM 110, wherein the SRAM 110 is implemented in an integrated circuit 100. The integrated circuit 100 further comprises a random logic 120 which is powered by a supply voltage VDD. The SRAM 110 comprises a memory array 111 with a plurality of memory cells, a level shifter 112, a word line (WL) decoder 113 for decoding the address signals to obtain the predecode signals, a control unit 114 for controlling the read/write operations, and an input/output (I/O) unit 115 for receiving and transmitting data between the SRAM 110 and the random logic 120. Besides, there could be address, clock, read/write control signals running between the control unit 114 and the random logic 120. In order to avoid read/write failure for the SRAM 110, the memory array 111 is powered by a supply voltage CVDD higher than the supply voltage VDD. The word line decoder 113, the control unit 114 and the I/O unit 115 are powered by the supply voltage VDD so as to save power. Therefore, the level shifter 112 is disposed between the word line decoder 113 and the memory array 111, which is used to change the voltage levels of signals generated by the word line decoder 113 from the supply voltage VDD level to the supply voltage CVDD level, so as to drive the memory array 111.
FIG. 2 shows a word line driver array 200 with a plurality of dual power rail drivers, wherein the word line driver array 200 is coupled between a word line decoder 202 powered by the supply voltage VDD and a memory array 204 powered by the supply voltage CVDD. The word line decoder 202 provides a segment signal Ssegment indicating that one section of the SRAM corresponding to the address signals has been selected. The word line decoder 202 further provides a plurality of predecode signals (ex. predecode[0], predecode[1], predecode[2] etc.) to the word line driver array 200 according to the address signals. Each dual power rail driver generates a word line signal according to the corresponding predecode signal and the segment signal Ssegment. For example, when the segment signal Ssegment is asserted, the driver 210 generates a word line signal WL[0] according to the predecode signal predecode[0], the driver 220 generates a word line signal WL [1] according to the predecode signal predecode[1], the driver 230 generates a word line signal WL[2] according to the predecode signal predecode[2] and so on. In the word line driver array 200, each word line driver has a level shifter, such as a level shifter 212 of the driver 210, a level shifter 222 of the driver 220 or a level shifter 232 of the driver 230, wherein each level shifter is disposed in data transmission path. Therefore, layout area and extra gate-delay in the critical timing path are increased, thus slowing access of the memory array.
FIG. 3 shows another word line driver array 300 with a plurality of dual power rail drivers, wherein the word line driver array 300 is coupled between a word line decoder 302 powered by the supply voltage VDD and a memory array 304 powered by the supply voltage CVDD. Compared with the word line driver array 200 of FIG. 2, no level shifter exists in data transmission path for each word line driver in the word line driver array 300, thereby the layout area of the word line driver array 300 is smaller than that of the word line driver array 200 of FIG. 2. However, a level shifter 306 disposed in the segment signal transmission path is used to change the voltage levels of a segment signal Ssegment generated by the word line decoder 302 from the supply voltage VDD level to the supply voltage CVDD level. Therefore, an extra gate-delay in the critical timing path is increased, thus slowing access of the memory array.